410803 Printing Organic Semiconductors for Logic Circuits with Low Patterning Errors and Electrical Variability

Wednesday, November 11, 2015: 4:45 PM
251D (Salt Palace Convention Center)
Gaurav Giri, Chemical Engineering, Massachusetts Institute of Technology, Cambridge, MA, Steve J.H. Park, Stanford University, Stanford, CA and Zhenan Bao, Chemical Engineering, Stanford University, Stanford, CA

Logic circuits are necessary to fulfill the vision of low cost, large area organic electronics, made with organic semiconductors (OSC) as the charge transfer layer. However, these circuits have stringent requirements. Primarily, all the thin film transistors (TFTs) participating in the circuit need to have a low variation in charge transfer characteristics (charge carrier mobility, threshold voltage, current, etc.). Additionally, organic circuits should be operated with low power consumption. To this end, research is being performed to pattern OSCs on the organic circuit to reduce parasitic current leakage. These twin requirements of low variability and OSC patterning set up conflicting goals, as the variability increases if each TFT is patterned individually. Moreover, patterning TFTs such that every TFT works, for the numerous TFTs required for logic circuits, is difficult with conventional methods such as ink jet printing due to patterning errors over large areas.

Here, we show a self-patterning method that does not require an extra patterning step to deposit the OSC layer onto the organic circuit. We have developed a surface functionalization procedure for a variety of oxide and metal surfaces, which, when paired with controlled solvent flow, can pattern OSCs in the TFT channel region only. Using this method, we show 100% viability of the patterned TFTs with low variability of charge carrier mobility and current. This method has been used to form logic gates and other organic circuits.

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