High Density Memory Devices Using Self-Assembled Gold Nanoparticle Arrays As Floating Gates

Floating gate memory devices find applications in many portable electronic devices such as mobile phones, cameras, laptops etc. Floating gate memory devices consist of field effect transistor with dual gate architecture, namely, floating gate and control gate for its memory characteristics. Depending on the presence or absence of electrons in floating gate, memory state can be read as 0 or 1. Programming or erasing (P/E) operation is performed by controlling the flow of electrons from or to the substrate through the tunneling oxide. Until now, miniaturization was accomplished by the reduction of feature sizes with concomitant reduction of tunneling oxide thickness. However, with the feature size reaching sub-25 nm, further device scaling is hampered by: (1) significant cell-to-cell interference as the spacing between the floating gates has now become comparable to memory cell size, and (2) non-scalability of tunneling oxide thickness due to unreliable charge retention after several program/erase cycles. Use of nanoparticles as charge-trapping nodes will aid in both minimizing interference and enhancing reliability through compartmentalization of charges. Metal nanoparticles, in particular, gold nanoparticle arrays as floating gate will result in realizing superior endurance and retention characteristics, as it offers deeper potential well in comparison to its semiconductor counterparts. Thus, manufacture of next generation floating gate memory devices entails process development for fabricating large scale (wafer level), high density (~ 10¹² particle per cm^-2) ordered gold nanoparticle arrays.

Here, we present fabrication and electrical characterization of metal-oxide-semiconductor (MOS) capacitor using self-assembled gold nanoparticle arrays as floating gates. We will also show a simple and cost-effective approach for fabricating wafer scale (~ 3 inch), close-packed arrays of gold nanoparticle by drop-casting gold colloids containing small amounts of excess ligand molecules on water surface. We will present the device charging, endurance and retention characteristics using both capacitance-voltage and electrostatic force microscopic measurements. Salient features of the MOS capacitor include: (a) less device-to-device variability over cm scale (b) reduced power consumption (c) good endurance characteristics and (d) reliable charge retention characteristics. This approach can be readily integrated into existing fabricating facilities for manufacturing next generation non-volatile memory devices.