- 3:15 PM

Plasma Etching for Metal Gate Electrode Fabrication in Conventional and Sub-Threshold Transistor Integration

Steven A. Vitale, Jakub Kedzierski, Nisha Checka, and Craig L. Keast. Advanced Silicon Technology, MIT Lincoln Laboratory, 244 Wood Street, Lexington, MA 02420

The 45nm technology node is witnessing the introduction of high-k dielectric and metal gate materials into CMOS logic production, after about a decade of materials research and process development. Coincidentally, the emerging field of ultra-low power electronics is investigating the integration of metal gate materials with a completely different set of performance needs than those of high-performance CMOS logic. A discussion of the physical and electrical requirements of the gate materials for these two technologies will be presented, along with an introduction to the “gate first” vs. “gate last” integration approaches.

A key challenge of integrating high-k / metal gates is the plasma etching of the gate stack. Results from etching of dual work function band-edge CMOS logic gates will be presented, demonstrating the feasibility of “gate first” integration. Plasma etching results on blanket and patterned mid-gap metal gate stacks will also be presented, illustrating how the fundamentals of plasma chemistry and ion-enhanced etching can be used to develop new plasma processes enabling integration of novel gate stack materials.

*This work was sponsored by the Air Force under contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government.